1. Field of the Invention
The present invention relates generally to refresh control circuits for memories, and more particularly, to circuits for controlling a refresh operation of memories in a data drive system and a method of controlling the same.
2. Description of the Background Art
Use of dynamic random access memories (referred to as DRAMs hereinafter) as memory devices in various data processing systems require refresh processing of the memory devices in a finite cycle.
In a synchronous type system such as a microprocessor including a synchronous data processing device, such memory access as instruction fetch and data access is in general performed periodically in response to a reference clock signal. FIG. 10 shows two refreshing manners in the synchronous type system. For a first memory, a periodic refresh cycle is provided between periodic memory access cycles. In a second memory, memory access is carried in parallel with refreshing. This is referred to as hidden refresh. In such synchronization type systems, switching between memory access and refreshing or identification thereof is controlled based on a reference clock signal.
In some synchronous type systems, a refresh operation is carried out once for several memory access times but not for each memory access, and in others, refresh is carried out in a burst manner in a fixed cycle. A refreshing operation is cyclically performed in response to a reference clock signal in either system.
A data flow type system is also developed in which processing is carried out in accordance with a flow of data in synchronization with pulses. A data flow type system in which data flows periodically enables the similar processing for refreshing to that of the synchronous type system. In other words, this system allows periodic refresh control by using pulse input for transferring data or data transfer as a clock signal. A data flow type system using a simple pipeline allows the most similar processing. More specifically, one of the simplest refresh control methods is to provide a refresh cycle immediately after each periodic memory access cycle. In this case, however, this method should be adapted to prevent distortion of a data flow when refresh is carried out once for several memory access times as in the synchronous system or refresh is performed in a burst manner.
Both of the above-described systems require some pulse periodically input. Thus, refresh processing is achieved by the control for interposing a refresh cycle in response to the pulse and determining time allotment of an access cycle and a refresh cycle.
The above described synchronous system and the system with a periodic data flow enable activation of a periodic refreshing operation without contention with memory access by using a free running reference clock signal.
Of the data flow type system, a data driven type system (hereinafter referred to as a data driven system) has the following three operational characteristics with respect to refresh control.
(1) No reference clock signal exists.
(2) Data flows in accordance with the timing at which data to be processed is generated.
(3) Processing is carried out only when data to be processed is generated.
Therefore, refreshing processing should be carried out in the data driving system on the premise of the above-described characteristics. Application of the above-described refresh processing method in the synchronous type system or the system with a periodic data flow to the data driven system presents some problems.
As described in (1), the data driven system is not capable of activating periodic refreshing because there is no reference clock signal for use in a synchronous type system. This problem can be resolved by periodically activating refresh processing by using a peripheral circuit, for example.
In the data driven type system, however, memory access is carried out irregularly as described in (2) and the access timing cannot be anticipated. Therefore, even if a refresh cycle is periodically activated by the above-described method, memory access might be induced in the refresh cycle. In such a case, the memory access is ignored or the refresh cycle terminates halfway. As described in the foregoing, the above-described resolution has shortcomings.
One resolution to this problem is a method of synchronizing activation of a refresh cycle with memory access. For example, such method is presented as activating a refresh cycle at the end of a memory access cycle. However, memory access is induced only when data to be processed exists according to (3) above. Therefore no memory access is induced when no data to be processed exists. According to the above-described method for solving the problem, no refresh processing is performed when no memory access is induced. Therefore, when no data to be processed exists for a sufficiently long period of time with respect to a time interval of a refresh cycle, no refresh processing will be carried out for the corresponding long period of time. This does not meet the requirement of periodic refresh processing to be carried out. In view of the foregoing, the method of activating a refresh cycle in synchronization with memory access is not satisfactory.